1. Field of the Invention
This invention relates to a instruction queue control system of a data processor having a instruction queue, particularly to improvements in a system for controlling the number of pieces of instruction data present in an instruction queue of a data processor having an variable length instruction system.
2. Description of the Prior Art
A prior art instruction queue control system will now be described with reference to FIGS. 3 and 4. Referring to the Figures, reference numeral 1 designates an First In First Out (FIFO) register as memory means for fetching and temporarily storing fetched instructions and providing successive instructions in the order of their input. This FIFO register can realize a instruction queue. Reference numeral 11 designates an adder/subtracter for calculating the number of effective data pieces present in a instruction queue, and 3 a queue controller for controlling the operation of the instruction queue. The FIFO register noted above includes an input line 4, through which are input instructions from a instruction fetch section 40 for fetching instructions from an bus interface section (hereinafter referred to as bus I/F section 30), and an output line 5, through which are output instructions to an instruction decode section 50. The queue controller 3 constitutes part of a central processing unit (CPU) (not shown), and it is accommodated together with the other control sections in the CPU. The instruction fetch section 40 provides an input signal 6 representing the number of data pieces of a fetched instruction to the queue controller 3 and adder/subtracter 11, and the instruction decode section 50 provides an output signal 7 representing the number of data pieces of the instruction which are output from the FIFO register 1 to instruction decoder 50 to the queue controller 3 and adder/subtracter 11. The queue controller 3 outputs instruction data input-output control signal 8. Reference numeral 10 designates an output signal representing the number of effective instruction data pieces, and 12 an adder/subtracter control signal.
FIG. 4 shows the adder/subtracter 11. As is shown, it includes an adder 111 for adding the input signal 6 and prevailing number 114 of data pieces, a subtracter 112 for subtracting the number 115 of data pieces of the sum output of the adder 111 and an output signal 7 from each other and a latch 21 as holding means for holding the number 116 of data pieces of the difference output of the subtracter 112 as prevailing value and providing an instruction data piece number output to the adder 111 and queue controller 3. The adder 111 and subtracter 112 are controlled by the adder/subtracter control signal 12 from the queue controller 3.
In operation, an instruction to be executed is fetched by the instruction fetch section 40 from an external circuit (not shown) through the bus I/F section 30. The fetched instruction is controlled by the queue controller 3 and temporarily stored in the FIFO register 1 to be output to the instruction decode section 50. The fetched instruction is supplied to the instruction decoder section 50 for decoding and execution.
The number of effective data pieces is controlled as follows. It is assumed that the number of instruction data pieces which are fetched at a time is two words and the number of instruction data pieces provided to the instruction decode section 50 is 0, 1 or 2 words. By the term "word" is meant a suitable length for expressing an operation code and operand of instruction data. A case of updating the effective data piece number in a queue is now explained. It is assumed, that the number 114 of effective instruction data pieces in a prevailing queue, i.e., number of data pieces held in the latch 21, is "4", two words of instruction data are input, (number of input data pieces from the input signal 6 being "2"), and one word of instruction data in the queue is provided at a time to the instruction decoder 50 (the number of output data pieces from the output signal 7 being "1"). In this case, the adder 111 adds "4" as the prevailing data piece number 114 and "2" as the number of input data pieces from the input signal 6 under control of an adder/subtracter control addition signal 12a from the queue controller 3, that is, the sum output 115 becomes "4+2=6". Then, the output data piece number of "1" from the output signal 7 is subtracted from the sum output 115 to produce a difference output of "6-1=5". The value of "5" as the difference output 116 is latched as a new value of the number of instruction data pieces in the queue in the latch 21. The value "5" as the instruction data piece number is provided as effective instruction data piece number output signal 10 to the queue controller 3.
Since the prior art instruction queue control system has the construction as described above, for controlling the number of effective data pieces in the queue addition and subtraction have to be performed one after another, thus requiring long calculation time. In addition, the use of the adder/subtracter requires a great amount of hardwares.